The requirement of increasingly small design rule for complementary metal-oxide semiconductor (CMOS) processes conflict with the requirements of salicide (self-aligned silicide) processes because very shallow junctions lead to junction leakage. On the other hand, the salicide sheet resistance (rho) of the polysilicon gate increases quickly when the width of the polysilicon gate scales down to the deep submicron range, e.g. 0.25 .mu.m. The higher salicide sheet rho of the polysilicon gate reduces circuit speed.
U.S. Pat. No. 5,817,558 to Wu describes a semiconductor processing method for forming self-aligned T-gate lightly-doped drain (LDD) device having a recessed channel. An oxide layer is formed over a substrate followed by forming a nitride layer over the oxide layer. The nitride and oxide layers are etched to expose the underlying substrate and to define a gate region. Polysilicon spacers are formed of the side walls of the nitride layer then an anisotropic etch is used to etch the sidewall spacers and the exposed substrate to form a T-shaped groove. Amorphous silicon is deposited, filling the T-shaped groove then the excess amorphous silicon and the nitride layer is removed to form a T-gate.
U.S. Pat. No. 5,621,233 to Sharma et al. describes electrically programmable read-only memory cells having T-shaped floating gates and control gates that surround almost all of the T-shaped floating gates except those that lie on a gate dielectric layer.
U.S. Pat. No. 5,940,697 to Yoo et al. a method for forming a T-gate structure in a metal-semiconductor field effect transistor (MESFET) that includes dielectric lift-off steps.
U.S. Pat. No. 5,559,049 to Cho describes a method of manufacturing a semiconductor device having a T-shaped gate electrode. Auxiliary gates are capacitively coupled with the T-shaped gate at undercut portions below both sides of the T-shaped gate.
U.S. Pat. No. 5,688,704 to Liu describes a method of fabricating an integrated circuit having a T-shaped polysilicon gate that facilitates the formation of rectangular-shaped silicon nitride spacers.
U.S. Pat. No. 5,783,479 to Lin et al. describes a structure and method for fabricating field effect transistors (FETs) having T-shaped gates that can reduce the parasitic resistance of the gate and source/drain.